A common method of generating clock signals in high-frequency systems, including microprocessors systems operating in the GHz frequency range, is to use a phase-locked-loop (PLL) or a delay-locked-loop (DLL). A typical DLL employs a variable delay block in which the delay time depends on a digital code applied to the delay block. DLLs are simple to design using a digital design methodology, but they do not provide good range, and they are susceptible to different types of noise. One noise source is jitter in the least significant bit (LSB) of the digital code around the lock condition. The LSB itself might not be uniform across the range of operation. If, for example, the DLL is nearing lock at a frequency where the LSB is large, the associated jitter will also be large. Compounding this problem is jitter caused by power supply voltage (Vcc) variationsxe2x80x94particularly bad at low power supply voltages.
FIG. 1 shows a typical prior art delay cell that is based on transistor gate capacitance loading in the signal path. The delay is controlled by the control signal C1 which connects the gate capacitance of MP2 to the signal path through MP1 when C1 is high. Such xe2x80x9cRCxe2x80x9d delay cells take up considerable die area, and are difficult to design for small ( less than 100 ps) delays.
Frequently, a cascade of delay cells are used as the delay block. That is, a series of delay cells are arranged so that the output of each delay cell serves as the input to the next delay cell. FIG. 2 shows a prior art DLL in which the delay block includes a cascade of xe2x80x9cnxe2x80x9d delay cells such as those shown in FIG. 1. The delay cells are controlled by a digital code that is represented by code signals C1, C2, . . . Cn from a counter which is incremented and decremented by an up/down control signal from a phase detector. A problem with the circuit of FIG. 2, however, is that the jitter from each of the cells sums cumulatively.